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LSI Layout Design Service
With System on Chip (SoC) design technique and the progress of new generation process technology, the chip complexity and large scale with multimillion-gate design makes long design time. In contrast, the design requirements are more addressed on higher performance, smaller area, lower power consumption, better manufacturability, faster time-to-market and lower design cost.
In order to response the challenges of present LSI design, we adopt several approaches to improve design quality with the unique implementation methodology and flow, and layout design schedule management. Using NovelChip systematic design flow – building on error-prediction methodology – preventing introduction of design errors especially for the changes that will be made late in design phase, the design closure can be quickly achieved by reduction of design iterations (Figure 1).
Figure 1. Reduction of total design time with NovelChip layout implementation methodology
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Improve Design Quality by Phasing Chip Designing
At first, with cooperated with customer at early step of chip development to synchronize front-end design, we start design prototype using temporary RTL or temporary netlist. The prototype focuses on prediction of timing closure, layout routing closure, and power consumption. The results of prototype are giving the solution to solve timing issues, studying floorplan to estimate chip size, and proposing power design style (Figure 2) to reduce power consumption and IR-drop. With the layout prototype study, the chip target becomes definite which can help to reduce requirement changing on layout and reduce design iteration. Also, the prototype can help to improve chip quality with quickly layout feedback and reduce total design time, and make the customer to easily control the whole development schedule and chip cost. At the same time, we can deeply understand the requests on layout and response customer's netlist release to quickly feedback layout result.
Secondly, we do layout confirmation for all release of temporary RTL/netlist of chip development with layout approach which agreed by both front-end and back-end designs. With the feedback of addressed items from physical design point of view, the customer can achieve high design quality and precise schedule control.
Thirdly, when final RTL/final netlist is released at completion of front-end chip development, the layout design is also be at final step to do final run With NovelChip methodology, just executing implementation flow which is developed and confirmed by synchronizing with front-end design, the layout design will be completed. The interim layout result came comes the RTL/netlist before final release will not be used in final run any more, that make layout designers possible to accept the final RTL/netlist release just 10 days before the end of physical design – signoff.
Figure 2. NovelChip RTL2GDSII implementation flow
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Reduce Design Time by Defining Clear Requirements on Layout Design
NovelChip methodology also focuses on getting common understanding with customer on the expectation and quality of layout deliverables. It helps to reduce the risk of misunderstanding on layout design requirement. Before staring physical design, we get customer’s requirements on layout design, deliverables quality and signoff criteria with check list. The preliminary survey with prototype clarifies the layout target and helps to address layout challenges. In addition, as we and customer both have common expectation on layout design deliverables, customer can also predict layout design time and design cost at beginning.
Improve Accuracy of Layout Design Scheduling by Automating and Standardizing Flow
NovelChip layout flow use unique timing optimization method to optimize timing and clear SI (signal integrity).The automated and standardized layout design flow has been confirmed and validated by many chip designs of various applications. It gives an effective design solution for high speed design with tough timing circuit. By only adding user’s special requirements and chip dependent specification to verified standardized design flow, it can schedule layout design with high accuracy and reduce total design time. In addition, with our experiences on logic design and layout design, and engineers’ skill on software development, we can develop utilities to implement customer requirements to layout to cover any missing function of P&R tool.
Manage Design Risk by Data Management and Version Control System for Layout Design
As same as software development, out design flow also manage layout input data, layout result with data management and version control system. Customer design requirements are recognized automatically by our design environment and data management tool, and used to check final layout result automatically. In addition, design data management system and version control system can easily trace customer released design data, difference of design specification and any interim layout result. With the systems, the executable chip design flow can be generated automatically and easily at completion of layout design. The layout implementation flow can be reused for the variety of derivative products and/or variety of similar products. Also, the total design time can be reduced significantly by using the verified implementation flow for similar layout requirement.
Figure 3. Reduce design risk with design data management and version control system
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